In many applications there is the need to measure one or, usually, more low frequency analog signals. This is for example the case of mobile communication terminals, where there is often the need to measure several operating parameters, such as the charge level of the battery, the temperature of the battery, the status of the connection to an external device, etc. Usually the analog signals that have to be measured are low frequency signals (for example from 0 to 500 Hz). A general purpose ADC (in short GPADC) is often used to convert the above mentioned signals from the analog to the digital domain while measuring them. In particular, SAR (Successive Approximation Register) analog to digital converters are widely diffused in the above applications due to the fact that such converters are particularly suitable for converting multiple signals at a conversion rate which is relatively low, for example of about 100 ksamples/second. An example of a switched capacitances SAR analog to digital converter is disclosed in U.S. Pat. No. 7,190,300.
SAR analog to digital converters are based on a conversion algorithm that, bit by bit, determines the output digital code, starting from the most significant bit (MSB) up to the least significant bit (LSB). After an initial phase called sampling phase, during which sample of the input signal is stored into the converter, each bit is determined during a cycle, also called SAR cycle, comprising a tentative voltage setting phase and a subsequent comparison phase. The latter is generally performed through an analog comparator. It is well known to a man skilled in the field that the comparison of the last SAR cycle, i.e. the cycle in which the LSB is determined, is particularly critical because the converter is stressed to the outmost, mainly but not exclusively from the point of view of the settling time. In such comparison, the comparator has to compare two voltages having a difference smaller than an LSB. Even the noise produced in the converter by different sources is a factor that affects in particular the comparison performed in the last SAR cycle.
As is well known to a man skilled in the field of SAR analog to digital converters, the above mentioned last comparison is not the only critical one, because there is always an additional critical comparison occurring on one of the previous N−1 comparisons. It is not possible to foresee in which SAR cycle such additional critical comparison takes place.
In order to achieve an effective resolution of N bits for the SAR analog to digital converter it is very important to perform correctly the two above mentioned critical comparisons. Such critical comparisons may be negatively affected by settling time of analog blocks of the ADC and by noise coming from different sources such as: the reference voltage buffer, the comparator, the capacitive array (KT/C noise).
The paper “An 820uW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90 nm Digital CMOS”, V. Giannini et Al., ISSCC Dig. Tech. Papers, pp. 238-240, February 2008, addresses the problem of the influence on the resolution of the ADC of the two above mentioned critical comparisons.
The paper in particular discloses an algorithm in which another SAR cycle (the (N+1)th) is added at the end of the classical SAR algorithm. The additional SAR cycle is added with the aim of correcting a possible error occurred in the previous N comparisons. The additional SAR cycle is redundant: it's aim is not to increase the number of bits of ADC resolution. According to the disclosure of the paper, the algorithm controller takes into account the result of the Nth comparison, and, relying on such result, understands whether the digital result of the classical SAR algorithm, obtained after the Nth cycle, is a round up or a round down of the ideal value of the input voltage. If it turns out to be a round up value, the controller generates a tentative for the (N+1)th comparison that is the round down or vice versa. The advantage of this comparison addition is that the critical comparisons, can be corrected (if such comparison was wrong by an error lower than 1 LSB) through the (N+1)th SAR cycle. In order to obtain this, the approach disclosed in the paper is the following:                the SAR cycle, and consequently the comparisons, from the 1st to the (N−1)th are performed using a low-consumption noisy comparator; and        the Nth and (N+1)th SAR cycle, and consequently the corresponding comparisons, are performed using a different high-consumption low-noise comparator.        
The prior art solution disclosed in the above paper has a drawback due to the fact that the effectiveness of the error correction algorithm is mainly restrained to the comparators' noise which, in many cases, is not the dominant noise contribute in a SAR ADC. For example, the noise of voltage buffer(s), provided for supplying internal reference voltage(s) needed to perform SAR cycles, is not taken into account. This contribute, along with KT/C noise, is not reduced at all by the approach disclosed in the above indicated paper.
Furthermore, the fact that there two different comparators are required has a design cost that is not negligible. In fact, the matching (for instance between two different offset performances) of the configurations of the two comparators becomes a critical aspect from converter linearity point of view. Moreover, the provision of two comparators increases the cost in terms of area and power consumption.